The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to a structure and method of forming an active semiconductor device in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate.
A field effect transistor (“FET”) is a transistor that relies on an electric field to control the shape and ultimately the conductivity of a channel in a semiconductor material. FETs usually have three terminals, known as the gate, the drain and the source. The voltage applied between the gate and source terminals modulates the current between the source and drain terminals. There are two different types of FETs, a p-type FET or “PFET” and an n-type FET or “NFET”. The voltage applied to the gate of a FET can increase the current flow from source to drain, or decrease the current flow from source to drain accordingly. In this way, when a gate voltage is applied to both an NFET and a PFET at a given value, one type of FET will be off, that is, not conducting, and the other type of FET will be on and conducting. The channel region of the FETs are either doped p-type to produce an NFET or doped n-type to produce a PFET.
The FETs in CMOS circuits can be provided in a bulk substrate or preferably in a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate. In a SOI substrate, active devices such as transistors and diodes are provided in a relatively thin single-crystal semiconductor layer that is separated from a bulk region of a substrate by an insulating layer. When field effect transistors (FETs) are formed in SOI substrates, faster switching operation is often achieved than otherwise. This is due to the fact that junction capacitance between the drain junction of the transistor and the bulk substrate is significantly reduced.
The amount of current that is conducted by a transistor when turned on can be increased greatly when a stress of sufficient magnitude is applied to the channel region of a transistor to induce a strain in the channel region. A variety of materials and techniques can be used to induce such stress. For example, in a substrate in which the active semiconductor region consists essentially of a single-crystal semiconductor such as silicon, a beneficial stress can be applied to the channel region of a FET by providing stressed regions of silicon germanium (“SiGe”) in portions of the source and drain regions of the FET at edges of the channel region.
Referring to FIG. 1, a graph is provided which depicts a magnitude of stress applied by such SiGe regions to the channel region of a FET as a function of thickness of the SiGe regions. As best seen in the graph, the negative value of the stress (“Sxx”) decreases monotonically, i.e., the magnitude of the stress applied to the channel region increases monotonically with the thickness (“tSiGe”) of the SiGe regions. Clearly, within the range of depths shown in FIG. 1, the deeper that SiGe regions extend below the surface of the substrate, the greater the amount of stress is applied to the channel region of the FET.
Unfortunately, in SOI substrates, the thickness of SiGe regions adds to the total thickness of the SOI layer. For low junction capacitance characteristics, the source/drain implants must be designed to abut the buried oxide. When the SOI thickness becomes large, this becomes difficult to achieve without also undesirably implanting the channel region underneath the gate with the dopant used to implant and define the source/drain regions. Referring back to the problem of silicon thickness affecting short polysilicon gates, an example can be used. Let us assume that ordinarily the height of the polysilicon gate or Hpoly is around 100 nm in thickness, and the silicon thickness (Tsi) is at 70 nm. If the Tsi is increased to 100 nm to 120 nm range to achieve strong stress benefits associated with SiGe, then the implant design for this improved thickness and dopants also causes penetration of the polysilicon gate and counter-doping of the channel region below the gate with the source/drain implants (e.g., n-type dopant being undesirably implanted into the p-type doped channel region of the NFET)
Accordingly, it would be desirable to provide a structure and method for fabrication of transistor devices with extended and increased dopant depth that does not affect the channel region of these transistors.